[sac-user] Porting of SAC compiler on FPGA
S.Scholz at hw.ac.uk
Wed Apr 18 18:13:20 CEST 2018
Compilation to LLVM-IR should be trivial as we generate C code as intermediate code….
transforming LLVM-IR into HDL is a different matter altogether. You may be able to use some
high-level synthesis tool such as C-to-Verilog but I doubt that a) it will always be able to deal
with the IR generated from the C code generated from SaC b) the generated hardware
would be particularly efficient.
Most likely, one would have to tweak the C code generated from SaC sources….
but it would surely be an interesting experiment!
It should be possible to generate LLVM-IR by simply installing our compiler distribution
and then using LLVM as C compiler. This can be rather trivially achieved by manipulating
a single resource file….
Our user mailing list (sac-user at sac-home.org<mailto:sac-user at sac-home.org>) (CC’ed) will surely be able to help efficiently on questions
regarding how to leverage the resource file once you / your students have the compiler installed…. :-)
On 18 Apr 2018, at 15:59, Rosario Culmone <rosario.culmone at unicam.it<mailto:rosario.culmone at unicam.it>> wrote:
We thought two steps: form SAC to LLVM-IR and then from LLVM-IR to VHDL or HDL. It would seem that LLVM-IR is a Static Single Assignment so the translation from SAC to LLVM-IR could be benefited. Also from LLVM-IL to HDL, it could be not very difficult.
It could be interesting to be able to collaborate maybe by sharing the load. We can use students in thesis or on specific projects. Greetings
2018-04-18 16:30 GMT+02:00 Hans-Nikolai Viessmann <hans at viess.mn<mailto:hans at viess.mn>>:
Some steps have already been made towards generating code for FPGAs, but
more work is still needed. If you like, I suggest that speak with my
supervisor and project leader for the SAC compiler, Sven-Bodo Scholz (CC'd).
On 04/18/2018 03:06 PM, Rosario Culmone wrote:
> Rosario Culmone
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